1. Field of the Invention
The present invention relates to the field of integrated circuits in general and, in particular, to circuits that test the integrity of said integrated circuits.
2. Prior Art
The use of integrated circuit technology for packaging circuit chips is well known in the prior art. A conventional integrated circuit chip includes a substrate on which a plurality of on-chip logic and other circuits are provided. The circuits cooperate to provide functions specific to the chip. The on-chip circuits include Receivers that receive signals from off the chip and Transmitters and/or Drivers for forwarding signals off the chip.
Analog Differential Receivers are one type of receivers used on integrated circuit chips. The invention described hereinafter is particularly concerned with chips using Analog Differential Receivers. Analog Differential Receivers rely uponxe2x80x9cdifferential pairxe2x80x9d signaling in order to operate. Differential pair signaling requires two physical signals of different voltage levels to be transmitted to the Differential Receiver in order to facilitate the transfer of a single bit of information. The logical state of the information bit at the output of the Differential Receiver is usually represented by the difference in voltage levels between the input signals.
As a consequence, Differential Receivers rely on their inputs to be different by a few 100 millivolts and centered around some midrange voltage to produce the correct output. If one of the inputs to the Differential Receivers is stuck at one of the voltage supplies (GND, VDD, VDD2, etc.) through a short, or is at a metastable state due to an open circuit, or is shorted to another signal, the outputs will be indeterminate.
U.S. Pat. Nos. 4,782,300 and 5,287,386 use discrete components, including resistors, for detecting open in transmission lines. Even though these systems may operate satisfactorily for their intended purposes, they are only effective at a board system level rather than the module or wafer level. In addition, these patents do not address stuck-at fault conditions which can cause problems in integrated circuits.
The IBM(copyright) CMOS 5S Data Book describes a system that detects if both Pad and Padn lines are open. The system described in the IBM CMOS 5S Data Book deviates from the invention set forth below in three main areas. First, the use of an XNOR or XNOR allows the designer to discriminate dynamically between valid and invalid conditions during functional use. Therefore, this circuit could be used functionally to avoid processing transient invalid conditions on the Pad/Padn lines (i.e., the same value on both lines) that could cause improper operations in a circuit. Second, our circuit is degateable, removing the capacitive loading and high speed noise from a functional circuit. Finally, our circuit is more testable than the circuit described in the prior art when using a limited-resource manufacturing tester, whereby only a portion of the possible circuit input and output pins are connected to the manufacturing tester. This is accomplished, through the use of two I/O wrap drivers; whereas, the prior art uses only one.
As a consequence, there is a need to provide a test circuit which addresses stuck-at fault conditions and open circuit conditions. In addition, the test circuit should be able to detect fault conditions at different stages (wafer level, module level or full I/O contact levels) of chip manufacturing process. This would allow the early elimination of defective chips prior to their being shipped to the field or used in products. By doing so, the overall cost of the machine would also be lowered, since the yield of chips from a particular line could be accurately determined and cost for removing defective chips from machines already in the field would be eliminated.
An in situ test circuit, fabricated on the integrated circuit chip, detects defects in the inputs to a Differential Receiver on the chip. The test circuit includes a pair of Pull devices; one of each coupled to one of the differential pair inputs. A pair of Pass Gate devices, one of each is coupled to one of the Pull devices and one of the differential pairs inputs. An exclusive NOR (XNOR) circuit arrangement is coupled to each of the Pass Gate devices. A first control signal is connected to the Pass Gates which isolates the test circuitry from the Differential Receiver. A second control signal is connected to the Pull devices. By applying a test pattern to the differential pairs and monitoring the output of the XNOR circuit arrangement, defects in the differential pairs can be determined.
In an alternate embodiment, a fault detection circuit is provided for each Differential Pair inputs to the integrated circuit.